1. Field Of The Invention
This invention pertains to transistors, and more specifically to a field effect transistor having its gate electrode located in a trench and being suitable for use in integrated circuits or as a discrete component, especially for use as a power transistor.
2. Description Of The Prior Art
Field effect transistors (FETs) are well known, as are power MOS (metal oxide semiconductor) field effect transistors (MOSFETs); such transistors are often used for power applications, i.e. where high voltage is applied. There is a need for power MOSFET transistors with very low on-state resistance (R.sub.DS (on)) for applications where high voltage must be switched. For instance, for a power supply for an integrated circuit, an output rectifier supports 20 volts for a 3.3 volt output and 10 volts for a 1.5 volt output. Typically, Schottky rectifiers are used but these disadvantageously have forward voltage drops of about 0.5 volts, which degrades the efficiency of the power supply.
A power MOSFET should have the lowest possible on-state specific resistance to minimize conduction losses. On-state resistance is a well known parameter of the efficiency of a power switching transistor and is a ratio of drain to source voltage to drain current when the device is fully turned on. On-state specific resistance refers to resistance times cross sectional area of the substrate carrying the drain current.
A typical prior art N-channel trenched MOSFET is shown in FIG. 1a, having conductive gate electrode 10 typically being N doped polycrystalline silicon (N type polysilicon) which is doped to be conductive serving as a gate electrode and located in a trench 12, the floor and sidewalls of which are insulated by a layer of gate oxide 16. Oxide layer 18 insulates the upper portion of gate electrode 10. The metallized source contact 20 contacts both the N+ doped source region 24 formed in the upper portion of the device and the P doped body region 38. The drain electrode 28 is a metallized contact to the N+ drain region 30 at the bottom surface of the device.
Formed overlying the N+ drain region 30 is an N- doped drift region 34 typically formed by epitaxy (hence an epitaxial layer) and being the drift region. The upper portion of the epitaxial layer is P doped to form the body region 38 and the very upper portion of the epitaxial layer is N+ doped to form the source region 24. It is to be understood that this transistor is typically formed in a silicon wafer and moreover there are a number of gate trenches 12 arranged (in a plan view) in rectangles, circles, hexagons, or linear structures, each defining a cell and all cells typically having a common source contact and a common gate contact.
In this case, to achieve high blocking capability, the trench 12 extends only partly through the N- doped drift region 34 and does not extend into the N+ doped drain region 30. The blocking state (off-state) is ordinarily the state when the transistor is off, i.e. not conducting current, and a measure of blocking capability is leakage current. Ideally, leakage current is zero. This transistor has an inferior on-state specific resistance to the ideal due to the substantial resistance of the N-doped drift region 34 below the trench.
An improvement over the prior art MOSFET of FIG. 1a is shown in FIG. 1b, which shows an N-channel device called the ACCUFET as described in "The Accumulation Mode Field Effect Transistor: A New UltraLow On-Resistance MOSFET" by Baliga et al., IEEE ELECTRON DEVICE LETTERS, Vol. 13, No. 8, August 1992.
The ACCUFET is an ultra-low on-state specific resistance vertical channel power MOSFET structure which uses current conduction via an accumulation layer formed on the surface of the trench gate structure. The ACCUFET does not contain a P body region 38, unlike the transistor of FIG. 1a, and the gate trench 42 extends all the way into the highly doped drain region 30. To achieve blocking the polysilicon is P doped and the N-region 34 is very lightly doped. For instance, the optimum N- drift region doping for a conventional MOSFET of FIG. 1a is typically 2.times.10.sup.16 /cm.sup.3, while in the ACCUFET the N- region doping is typically below 10.sup.14 /cm.sup.3. The doping type of the conventional MOSFET polysilicon gate electrode is typically N-type, and not P-type. The ACCUFET on-state specific resistance is 105 micro-ohm cm.sup.2 at a gate bias of 15 volts. Thus the ACCUFET is described as having an on-state specific resistance which is the lowest attainable for any known MOS gate-control device. Moreover, the ACCUFET is bidirectional, i.e. reversal of the source and drain contacts in use is available.
However, the ACCUFET blocking characteristics are less than might be desired, and negative gate voltages are required to reduce leakage current to acceptable levels.
Thus, it would be desirable to improve performance over both the prior art MOSFET of FIG. 1a and the ACCUFET of FIG. 1b in terms of the combined parameters of on-state specific resistance and blocking characteristics.